1. Field of the Invention
The present invention relates generally to modulators and a modulation method, and more particularly, to modulators for modulating MSK (Minimum Shift Keying) signals and a method therefor.
2. Description of the Background Art
Modulation techniques for converting a signal to be transmitted into a signal having a pattern adaptable to a transmission medium and for restoring the transmitted signal to the original pattern are important in the field of communication. In recent years, digital data is often used as a signal to be transmitted. Various digital modulation systems have been proposed to modulate such digital data for transmission in the field of radio communication. The MSK is one of such digital modulation systems.
MSK is included in continuous-phase FSK (Frequency Shift Keying), one of the frequency modulation techniques. The continuous-phase frequency shift keying is a frequency modulation method in which the frequency of a modulated wave is switched between predetermined values with the change of a carry frequency being continues at the switching. The continuous-phase FSK with modulation index of 0.5 is called MSK system. An instantaneous frequency of a modulated wave is ordinarily switched between two frequencies, one called a mark frequency fm and the other called a space frequency fs.
More specifically, the frequency of the modulated wave is switched to the mark frequency fm and the space frequency fs corresponding to the logical values "1" or "0" of the digital data to be modulated, respectively, on the MSK system. According to the frequency modulation technique with the amplitude of a modulated wave fixed, a signal modulated (MSK signal) by such MSK is less affected by non-linear distortion at the time of transmission.
For demodulating the MSK signal, a mark frequency component and a space frequency component are extracted from the MSK signal to perform synchronous detection by using the extracted mark frequency component or space frequency component, thereby detecting the change of the instantaneous frequency of the modulated wave from the carrier frequency, which is the so-called deviated frequency-locking synchronous detecting scheme.
FIG. 4 is a block diagram showing the structure of a conventional MSK signal demodulation circuit for demodulating an MSK signal by using the deviated frequency-locking synchronous detecting scheme. The structure and operation of a conventional MSK signal demodulation circuit will be described in the following with reference to FIG. 4.
With reference to FIG. 4, an MSK signal received at an input terminal 10 is applied to detectors 11 and 12. The detectors 11 and 12 quadrature-detect the MSK signal in synchronism with the output of a voltage-controlled carrier oscillation 15.
More specifically, the detector 11 multiplies the MSK signal by the output of the voltage-controlled carrier oscillator 15 and the detector 12 multiplies the MSK signal by the output of a 90.degree. phase shifter 16. The 90.degree. phase shifter 16 shifts the phase of the output of the voltage-controlled carrier oscillator 15 by 90.degree.. The MSK signal is detected in synchronism with each of the two signals differing in phase from each other by 90.degree..
The voltage-controlled carrier oscillator 15 is a variable output frequency oscillator using the central value of the output frequency as a mark frequency fm or a space frequency fs. It is assumed in the following that the center frequency of the output of the voltage-controlled carrier oscillator 15 is a mark frequency fm.
The MSK signal applied to the input terminal 10 is represented as the function Y (t) of time t expressed by the following equation. EQU Y (t)=cos [(.omega.c+ui.multidot..omega.d).multidot.t+.phi..sub.0 ](1)
In the above-described equation (1) .omega.c denotes a carrier angular frequency, ed denotes an angular frequency of 1/4 of a clock angular frequency, ui denotes a digital value (.+-.1) corresponding to either the logical value "0" or "1" of the original digital data before modulation and .phi..sub.1 denotes the initial phase (0 or .phi.). One bit of the original data before modulation has a fixed duration. The MSK signal, which is a modulated wave, therefore includes a frequency component with one cycle of one-bit duration, that is, a clock component. .omega.d is 1/4 of the angular frequency of the clock component. Since generality of the MSK signal is not lost even with the initial phase .phi..sub.0 =0, it is assumed in the following that Y (t)=cos [(.omega.c+ui.multidot..omega.d).multidot.t].
With fc denoting a carrier frequency and fd denoting 1/4 of the frequency of the clock component, the mark frequency fm can be represented as a sum of the two frequencies, that is, as fc+fd. The relation of .omega.m=.omega.c+.omega.d is established among a carrier angular frequency .omega.c, an angular frequency .omega.d of 1/4 of a clock angular frequency and a mark angular frequency .omega.m. The mark angular frequency .omega.m is an angular frequency of a modulated wave (mark signal) transmitted corresponding to the digital value of +1 and represents the angular frequency of the mark frequency component. The output of the voltage-controlled carrier oscillator 15 can be therefore be represented as the function C (t) of time t expressed by the following equation. ##EQU1##
In the above equation (2), .theta. denotes a phase error. A correct detection output can be obtained from the detector 11 only when the phase ((.omega.c+ui.multidot..omega.d).multidot.t) of the MSK signal coincides with the phase (.omega.m.multidot.t-.theta.) of the output of the voltage-controlled carrier oscillator 15. That is, the output signal I of the detector 11 is represented as the variable I (t) of time t expressed by the following equation. EQU I (t)=1/2 cos [(ui-1).multidot..omega.d.multidot.t+.theta.](3)
The 90.degree. phase shifter 16 shifts the phase of the output of the voltage-controlled carrier oscillator 15 by 90.degree.. The output of the 90.degree. phase shifter 16 is therefore represented as sin (.omega.m.multidot.t-.theta.), the function of time t. A correct detection output can be obtained from the detector 12 only when the phase ((.omega.c+ui.multidot..omega.d).multidot.t) of the MSK signal coincides with the phase (.omega.m.multidot.t-.theta.) of the output signal of the 90.degree. phase shifter 16. That is, the output signal Q of the detector 12 is represented as the function Q (t) of time t expressed by the following equation. EQU Q (t)=1/2 sin [(ui-1).multidot..omega.d.multidot.t+.theta.](4)
As described above, the output signal I of the detector 11 and the output signal Q of the detector 12 have phases different by 90.degree. from each other. In FIG. 2, the output signal I of the detector 11 and the output signal Q of the detector 12 are multiplied together by a multiplier 13. The output signal of the multiplier 13 will be represented as the function V.sub.t (.theta.) of time t and phase error .theta., which function is expressed by the following equation. EQU V.sub.t (.theta.)=1/8 sin [2 (ui-1).multidot..omega.d.multidot.t+2.theta.](5)
The output signal V.sub.t (.theta.) of the multiplier 13 is applied to a loop filter 14. The loop filter 14 removes an alternating current component of the output signal V.sub.t (.theta.) of the multiplier 13 to extract a direct current component only. That is, the loop filter 14 functions to remove the term of the angular frequency .omega.d at the right side of the equation (5). The output signal of the loop filter 14 will therefore be represented as the function V (.theta.) of phase error .theta. only, which is expressed by the following equation. EQU V (.theta.)=1/8 sin (2.theta.) (6)
The output signal of the loop filter 14 is applied to the voltage-controlled carrier oscillator 15 as a control voltage.
As described above, the voltage-controlled carrier oscillator 15 is constantly supplied with a control voltage having a level proportional to the phase error .theta., from the carrier component of the mark signal.
The voltage-controlled carrier oscillator 15 controls its output frequency in response to the control voltage. When the control voltage is higher than 0 V, the voltage-controlled carrier oscillator 15 increases its output frequency to bring the phase error .theta. near to 0. Conversely, when the control voltage is lower than 0 V, the voltage-controlled carrier oscillator 15 reduces its output frequency to bring the phase error .theta. near to 0. With the control voltage of 0 V, the voltage-controlled carrier oscillator 15 operates to prevent the output frequency from changing. When the phase error .theta. is 0 or .pi., therefore, the output frequency of the voltage-controlled carrier oscillator 15 is locked to a fixed value.
The demodulated digital data with the phase error .theta. of 0 is inverse to that with the phase error .theta. of .phi.. Differential coding is therefore performed on the transmission side when generating digital data before being modulated. The differential coding is a method of coding by which such operation is performed as establishing that y.sub.k =y.sub.k-1 .sym.x.sub.k (.sym.+ is an exclusive OR symbol) at all times, with x.sub.k representing data of k-th input data and y.sub.k representing the data of k-th output bit in a coder for generating the digital data to be modulated. The MSK signal obtained by modulating the digital data generated by the differential coding will therefore attain the original data before the differential coding without fail as a result of the reverse processing, performed at the demodulating circuit, of this differential coding irrespective of the phase error .theta. of 0 and .pi..
As can be seen from the equations (3) and (4), the output signals of the detectors 11 and 12 with the phase error .theta. of 0 will be respectively represented as the functions I (t) and Q (t) of time t expressed by the following equations.
In a case where a digital value ui=+1: EQU I (t)=1/2 EQU Q (t)=0
In a case where a digital value ui=-1; EQU I (t)=1/2 cos (2.omega.d.multidot.t) EQU Q (t)=1/2 sin (2.omega.d.multidot.t)
FIG. 5 is a waveform diagram showing the relationships between the output signals I and Q of the detectors 11 and 12 and the frequency of the MSK signal applied to the input terminal 10 and between the output signals I and Q and the digital data before being modulated. In this case, the phase error .theta. is 0.
It is assumed that the MSK signal with such a frequency change as shown in line (b) of FIG. 5 is applied to the input terminal 10. The digital value ui designated by the MSK signal takes -1 and +1 corresponding respectively to a space frequency fs and a mark frequency fm as shown in line (a) of FIG. 5. In this case, with the phase error .theta. of 0, the output signal I of the detector 11 becomes a fixed direct current signal in the periods T2, T3 and T6 wherein the MSK signal has the mark frequency fm and becomes an alternating current signal in the periods T1, T4 and T5 wherein the MSK signal has a space frequency fs as shown in waveform (c) FIG. 5. Similarly, the output signal Q of the detector 12 becomes a fixed direct current signal in the periods T2, T3 and T6 and becomes an alternating current signal out of phase, by 90.degree., from the output signal I of the detector 11 in the periods T1, T4 and T5. Each of the periods T1-T6 has a duration allotted to one-bit data of the MSK signal, that is, a duration equivalent to one cycle of the clock component. Each frequency of the output signal I of the detector 11 and the output signal Q of the detector 12 in each of the periods T1, T4 and T5 is half the clock frequency.
As described above, the MSK signal applied to the input terminal 10 has a mark frequency component reproduced by a so-called Costas-loop constituted by the detectors 11 and 12, the multiplier 13, the loop filter 14, the voltage-controlled carrier oscillator 15 and the 90.degree. phase shifter 16. The output signals I and Q of the detectors 11 and 12 which have detected the MSK signal in synchronism with the reproduced mark frequency component are applied to the multiplier 13 for reproducing the carrier component of the mark signal and are also applied to an amplitude discrimination unit 17 and a square circuit 19.
The amplitude discrimination unit 17 converts the signal I into a signal having such a rectangular wave as shown in waveform (e) of FIG. 5 by determining whether the amplitude of the output signal I of the detector 11 is equal to or above the level indicated by the broken line in waveform (c) of FIG. 5. The rectangular wave is applied to a timing determining unit 18.
The timing determining unit 18 converts the rectangular wave into a digital signal having a logical value of "0" or "1" ((g) in FIG. 5) by sampling the rectangular wave voltage from the amplitude discrimination unit 17 in response to a clock signal ((f) in FIG. 5) applied from a clock reproduction circuit 20 in a constant timing. The converted digital signal is decoded to the original digital data before being modulated by a differential decoding circuit 30.
The differential decoding circuit 30 includes a symbol delay circuit 31 and an exclusive OR circuit 32. The digital signal output from the timing determining unit 18 is directly applied to the exclusive OR circuit 32, while the same is delayed by one bit by the delay circuit 31 and applied to the exclusive OR circuit 32. The exclusive OR circuit therefore outputs an exclusive OR of the data of the adjacent two bits of the digital signal output from the timing determining unit 18. As a result, every time the timing determining unit 18 outputs one-bit data, a demodulated data output terminal 40 receives one-bit data having a logical value equivalent to an exclusive OR of the one-bit data and the one-bit data previously output from the timing determining unit 18. In other words, the digital signal reproduced from the MSK signal is subjected to the reverse processing of the differential coding performed at the time of transmission by the differential decoding circuit 30, to be decoded to the original data before being subjected to the differential coding.
The square circuit 19 squares the output signal Q of the detector 12 and applies the squared signal to the clock reproduction circuit 20. The output signal Q of the detector 12 is expressed by the equation (4) as the function Q (t) of time t. The output signal Q of the square circuit 19, with the phase error .theta. of 0, will be expressed by the following equation as the function Q.sup.2 (t) of time t accordingly. EQU Q.sup.2 (t)=1/4 [1-cos {2(ui-1).multidot..omega.d.multidot.t}](7)
The output signal of the square circuit 19, with the digital data ui of -1, will be expressed by the following equation as the function Q.sup.2' (t) of time t accordingly. EQU Q.sup.2' (t)=1/4 {1-cos (4.omega.d.multidot.t)} (8)
With .omega.d representing the angular frequency of 1/4 of the clock angular frequency, the alternating current component included in the output signal of the square circuit 19, with the digital value ui of -1, includes the clock frequency component only. That is, the square circuit 19 extracts the clock component included in the MSK signal by squaring the output signal Q of the detector 12.
The clock reproduction circuit 20 includes a PLL (Phase Locked Loop) constituted by a voltage-controlled clock oscillator 21, a phase detector 22 and a loop filter 23.
The phase detector 22 phase-detects the output signal of the voltage-controlled clock oscillator 21 by using the reference signal extracted by the square circuit 19 as a clock component. As a result, the phase detector 22 outputs a voltage having a direct current level proportional to a phase difference between the clock component extracted by the square circuit 19 and the output signal of the voltage-control clock oscillator 21. The output voltage of the phase detector 22 is smoothed by the loop filter 23 and applied to the voltage-controlled clock oscillator 21 as a control voltage.
The voltage-controlled clock oscillator 21 controls its own output frequency in response to the control voltage. The application of the output voltage of the phase detector 22 to the voltage-controlled clock oscillator 21 through the loop filter 23 locks the output signal of the voltage-controlled clock oscillator 21 to a signal having the same phase and the same frequency as those of the clock component extracted by the square circuit 19.
In this way, the clock reproduction circuit 20 reproduces a clock signal having a frequency corresponding to the duration of one bit of the digital data before being modulated, based on the clock component in the MSK signal extracted by the square circuit 19. The clock signal reproduced by the clock reproducing circuit 20 is applied to the timing determining unit 18. The duration of one bit of the digital signal output from the timing determining unit 18 becomes the same as that before being modulated as a result.
With the digital data ui=+1, the square circuit 19 outputs 0 and the phase detector 22 consequently loses a reference signal. With no reference signal applied to the phase detector 22, the voltage-controlled clock oscillator 21 is supplied with no control voltage to prevent locking of the frequency and the phase of the output signal of the voltage-controlled clock oscillator 21. The time period from the application of the reference signal to the phase detector 22 to the signal output of the voltage-controlled clock oscillator 21 in response to the reference signal, which period is the loop response speed of the clock reproduction circuit 20, is set to be sufficiently longer than the time period from the application of one-bit MSK signal to the input terminal 10 to the application of the subsequent one-bit MSK signal to the input terminal 10, that is, the data transmission speed by the MSK signal. In addition, such digital data as is transmitted through radio communication is usually scrambled at the transmission side so as to have the same frequency of the occurrence of the two logical values "0" and "1 ". It is therefore understood that it is not highly possible that the digital value ui of the MSK signal continuously attains +1 for a long time period. Thus, once the frequency and the phase of the output signal of the voltage-controlled clock oscillator 21 are locked in response to the digital value ui attaining -1, the frequency and the phase of the output signal of the voltage-controlled clock oscillator 21 do not deviate from those locked even if the digital value ui attains +1 thereafter.
The above-described circuit operation demodulates the MSK signal applied to the input terminal 10 to the original digital data which is output from the decoded data output terminal 40.
Although the foregoing is the description where the center frequency of the output of the voltage-controlled carrier oscillator 15 is a mark frequency fm, the same circuit operation can demodulate the MSK signal to the original data also in a case where the center frequency of the output of the voltage-controlled carrier oscillator 15 is a space frequency fs. A low-pass filter can be added in the subsequent stage to the detectors 11 and 12. The provision of a low-pass filter removes a small amount of undesired high frequency component included in the output signal I of the detector 11 and the output signal Q of the detector 12.
As described in the foregoing, a conventional MSK signal demodulation circuit includes a square circuit (the square circuit 19 in FIG. 4) to extract a clock frequency component included in an MSK signal. FIG. 6 is a circuit diagram showing an example of a common circuit for use as the square circuit.
The square circuit is constituted by such an absolute value circuit as shown in FIG. 6a, for example. The absolute value circuit outputs the positive full-wave rectification waveform .vertline.e.sub.i .vertline. of an input signal e.sub.i. The absolute value circuit includes two operation amplifiers OP1 and OP2 and two diodes D1 and D2 in general. The diode D1 is provided between the output end and the inversion input terminal of the operation amplifier OP1. The diode D2 is provided between the output and the inversion input terminal of the operation amplifier OP1 through a resistor R3.
The input signal e.sub.i is applied to the inversion input terminal of the operation amplifier OP1 through a resistor R1. With the input signal e.sub.i of having the negative polarity applied, the diode D1 conducts to produce a signal of the opposite polarity to that of the input signal e.sub.i at a node n between the resistor R3 and the diode D2. Conversely, with the input signal e.sub.i having the positive polarity applied, the diode D1 becomes non-conductive, while the potential at the node n is clamped at the forward threshold voltage of the diode 2. A half-wave rectification waveform is obtained at the node n, which waveform is the inversion of the phase of the component having the negative polarity of input signal e.sub.i. The half-wave rectification waveform is applied to the inversion input terminal of the operation amplifier OP2 through a resistor R4. The inversion input terminal of the operation amplifier OP2 also receives an input signal e.sub.i through a resistor R2. The operation amplifier OP2 with a resistor R5 connected between the inversion input terminal and the output terminal constitutes an adder for adding a signal applied to the inversion input terminal through the resistor R2 and a signal applied to the inversion input terminal through the resistor R4 at a ratio of 1 to 2. The output end of the operation amplifier OP2 therefore obtains a waveform with the input signal e.sub.i and the above-described half-wave rectification waveform added at a ratio of 1 to 2, that is, it obtains the full-wave rectification waveform of the input signal e.sub.i.
In addition, the square circuit can be constituted simply by a multiplier 190 as shown in FIG. 6b. In this case, the signal e.sub.i to be squared is used as both input signals IN1 and IN2 of the multiplier 190. The multiplier 190 multiplies the two input signals IN1 and IN2 together to obtain a signal (e.sub.i).sup.2 which is the square of the input signal e.sub.i, as the output signal of the multiplier 190.
As described above, the conventional demodulation circuit for demodulating an MSK signal includes a square circuit to extract a clock frequency component included in the MSK signal. Such an absolute value circuit as shown in FIG. 6a and such a multiplier as shown in FIG. 6b are generally used for the square circuit.
The absolute value circuit including two operation amplifiers, two diodes and many resistance elements, used as a square circuit, requires the increased number of components of the entire demodulation circuit. The cost of the demodulation circuit is increased accordingly.
With a multiplier used as a square circuit, while the number of components of the multiplier itself does not lead to a large increase in the number of components of the entire demodulation circuit, various additional circuits are required because of the operation characteristic of the multiplier. For example, since an output signal of the multiplier includes an undesired higher harmonic component, a low-pass filter or a bandpass filter is provided for suppressing the higher harmonic component in the succeeding stage to the multiplier in general. Some multipliers attaining a low level output depending on an input signal require an amplifier to be provided in a succeeding stage to the multiplier for amplifying the output signal. The multiplier, for use as a square circuit, also requires such additional circuits, thereby increasing the number of components of the entire demodulation circuit.